1. Field of the Invention
The present invention relates to a capacitor structure, especially a stepwise capacitor structure which represents a feature of multiple capacitors; and a fabrication method thereof, and a substrate employing the same.
2. Description of Related Art
An electronic circuit today, such as a computer, has powerful functions and an increasing processing speed. Along with an increasing operation frequency of the electronic circuit, the noises at the power terminal and the ground terminal thereof get more and more serious and anxious. In order to reduce the noises, a so-called decoupling capacitor is introduced and disposed between the power and the circuit.
In addition, the transient current required by a chip during the operation sometimes would be higher than the available current provided by the on-chip capacitors of the chip, which degrades the processing performance of the chip. To solve the problem, an off-chip capacitor is disposed at an appropriate position outside the chip or on the chip surface, wherein some circuit areas of the chip which may draw large transient currents are termed as ‘hot-spots’ hereinafter.
In general, the position for disposing a decoupling capacitor is preferably near to a die load or a hot spot as close as possible to enhance the performance. In particular, a decoupling capacitor is usually disposed on the die-side or the land-side of a chip. FIG. 1 is a cross-section diagram of an integrated circuit (IC) 104 with die side capacitors 106 and land side capacitors 108 in the prior art. As shown by FIG. 1, an IC 104 is disposed on a substrate 102. Die side capacitors 106 are disposed on the same surface with the IC 104, and land side capacitors 108 are disposed on opposite surface to the IC 104.
FIG. 2 is the equivalent circuit diagram of FIG. 1. The die load 202 herein represents some portions of the integrated circuit (IC) 104 which need currents provided by capacitors. The currents may be provided by an on-chip capacitor 204 of the chip 104, or by an off-chip capacitor 206 (for example, the die side capacitors 106 and the land side capacitors108 in FIG. 1). However, due to chip packaging, the capacitor 206 must be spaced from the die load 202 by a distance, which results in an inductance effect represented by an inductor 208. If the inductance (or impedance) of the inductor 208 is getting higher, the response speed of the capacitor 206 gets slower and the ability of noise-processing of the capacitor 206 is accordingly reduced. This means the ability of noise-processing of the capacitor 206 is reduced when the inductance (or impedance) of the inductor 208 is high. As a result, the circuit efficiency is significantly affected.
To overcome the above-mentioned problem, a hierarchical capacitor structure has been developed in another prior art. FIG. 3 is a cross-section diagram of a conventional hierarchical capacitor structure and FIG. 4 is the equivalent circuit diagram of FIG. 3.
Referring to FIGS. 3 and 4, a conventional hierarchical capacitor structure 300 includes three capacitor structures 302, 304 and 306. The capacitor structure 302 is defined by layers 311-315 (including both dielectric layers and conductive layers); the capacitor structure 304 is defined by layers 316-320 (including both dielectric layers and conductive layers); the capacitor structure 306 is defined by layers 321-325 (including both dielectric layers and conductive layers). The capacitor structures 302, 304 and 306 are electrically connected to the layers 311-325 through conductive vias 330, 332 and 334, and the coupling is shown by FIG. 3.
The capacitor structures 302, 304 and 306 are electrically connected to outside circuitry by the conductive vias 330, 332, 334 and a top connector 340 and a bottom connector 342.
The quantity of the conductive vias 330, 332 and 334 passing through capacitor structures may affect the effective capacitance and the effective inductance of the capacitor structures. In detail, more the conductive vias 330, 332 and 334, less the effective capacitance and the effective inductance of the capacitor structures are; longer the conductive vias 330, 332 and 334, greater the effective inductance of the capacitor structures is. Besides, by connecting in parallel the conductive vias 330, 332 and 334, the effective inductance of the capacitor structures would be reduced.
The equivalent circuit of the capacitor structure 302 includes a capacitor 408 and an inductor 420 is shown by FIG. 4; the equivalent circuit of the capacitor structure 304 includes a capacitor 410 and an inductor 422 is shown by FIG. 4; the equivalent circuit of the capacitor structure 306 includes a capacitor 412 and an inductor 424 is shown by FIG. 4, wherein the capacitance of the three capacitors are subject to: 412>410>408 and the inductance of the three inductors are subject to 424>422>420. Since the current rate of the capacitor is affected by the current path (i.e. the inductor), therefore, the current rates of the three capacitors are subject to 408>410>412. FIG. 4 is the diagram of the equivalent circuit for the conventional hierarchical capacitor structure in FIG. 3, wherein capacitor 404 represents an on-chip capacitor.
A combination of the capacitor 408 and the inductor 420 enables the capacitor 408 competent for suppressing high-frequency noise. Since the capacitor 408 has small capacitance, the available transient current (high frequency) provided by the capacitor 408 is not large.
The current rate of the capacitor 410 is slower than that of the capacitor 408, therefore, the capacitor 410 is suitable for suppressing medium-frequency noise; the current rate of the capacitor 412 is the slowest, therefore, the capacitor 412 is suitable for suppressing low-frequency noise only.
Note that when a die load draws current, it usually draws different currents from different conductive vias. For example, the die load draws large currents from nearer conductive vias and draws small currents from farther conductive vias. Accordingly, it suggests that assuming a number of conductive vias are disposed around a small capacitor structure (for example, 302 in FIG. 3), some of current-drawing points still may not contribute to reduce the expected effect of reducing inductance (since the conductive vias are not effectively connected in parallel). Therefore, the inductor-capacitor combination scheme of FIG. 3 (a large capacitor paired with a large inductor, and a small capacitor paired with a small inductor) may not function as expected. In addition, although the capacitor structure 304 is initially designed to be paired with the equivalent medium inductor 422, but the current path between the current-drawing point and the capacitor structure 304 is still too long, which makes the effective inductance of the capacitor structure 304 greater than the medium inductor 422, and the architecture of FIG. 3 fails to achieve the desired efficiency.
In other words, for the architecture of FIG. 3, only effectively parallel-connected conductive vias can effectively reduce the inductance; however, the architecture does not assure the conductive vias in effective parallel connection, which is a real obstacle to make the architecture function as a hierarchical decoupling capacitor structure.